A Hardware Realisation of a Block-based Disparity Estimator on a Cmos Sea-of-gates Semi-custom Chip

In this paper we describe a rst hardware realisation of a block-based disparity estimator which is suitable for real time applications with video speed. Since the quality of the calculated raw disparity elds will be rather poor, postprocessing steps are needed, but this is considered as a separate step. The circuit is implemented as an Application Speciic Integrated Circuit (ASIC) on a CMOS Sea-of-Gates (SoG) semi-custom chip. The image of the SoG-chip has been developed at Delft University of Technology (DUT) and the chip is metallized at the DUT processing facility DIMES. The objectives of the hardware realisation of a real time disparity estimator are to investigate the possibilities of the SoG-structure for video signal processing applications and to study which architectures of more complex disparity estimators are best suited for an ASIC implementation.